Multiple functions are today commonly being integrated onto a single system chip. When initially defining architecture for integration of multiple discrete components onto a single chip, access to external devices can be a critical issue. For example, an MPEG video decoder system often employs external memory for various data areas or buffers such as frame buffers. This external memory is typically implemented using either DRAM or SDRAM technology. In the decoder system, a video decode unit requires immediate access to external memory when needed to prevent starving the video display or on-screen graphics. If the video decoder's request for data is delayed, the picture could be corrupted. Likewise, an on-chip processor, if held from accessing external memory when needed could experience significant performance degradation.
In a typical approach for accessing off-chip devices, each on-chip functional. unit is given access to the needed external device(s) through a data bus dedicated to that particular unit. Although locally efficient for accessing an external device, globally within the integrated system this approach can be less than optimal. For example although each function might have complete access to its own external memory area, there is no shared access between functions of the integrated system. Thus, transferring data from one memory area to another memory area of the system is often needed. This obviously increases data transfers and can degrade performance of the overall system, i.e., compared with a shared bus/memory system. The problem can be particularly significant in attempting to enhance MPEG-2 decoder chip design, such as for inclusion in a "set-top box" chip.
As is well-known, the MPEG-2 standard describes an encoding method that results in substantial bandwidth reduction by a subjective lossy compression followed by a lossless compression. Encoded, compressed digital data is subsequently decompressed and decoded in an MPEG-2 decoder. Video decoding in accordance with the MPEG-2 standard is described in detail in commonly assigned U.S. Pat. No. 5,576,765, entitled "Video Decoder", which is hereby incorporated herein by reference in its entirety.
MPEG-2 video decoder chips have often been designed with data transfer units constructed for dedicated memory accesses. These data transfer units take requests from an arbiter unit internal to the memory controller macro of the decoder and process the requests directly as transfers to and from external dedicated memory, such as dynamic random access memory (DRAM).
In order to enhance existing MPEG decoder designs, however, it is desired to convert from dedicated bus accesses to external memory, to shared bus accesses to external memory. Within such a shared bus environment, the present invention provides an enhanced data transfer engine which allows intelligent pipelining of data transfers to/from, for example, a video decode unit onto the shared bus for transfer of data between the video decode unit and external memory.